The invention relates to a method of manufacturing an electronic device whereby a conductive layer is provided on an electrically insulating substrate, from which layer a conductor pattern is formed by means of a mask comprising a dielectric layer in which said pattern is defined by openings which were formed in the dielectric layer by means of lithography, which dielectric layer at the areas of the windows to be formed is provided with auxiliary windows having dimensions which are greater, at least in one direction, than the dimensions of the windows to be formed, whereupon an additional dielectric layer is provided which is etched back anisotropically without a mask such that of the additional layer spacers remain behind on side walls of the auxiliary windows. The invention is of particular importance for monolithically integrated circuits. In addition, however, the invention may also be of importance for other devices in which electrical conductors are provided at very small distances from one another, as will become clear from the description, such as, for example, PCBs, or control matrices for LCDs.
Such a method is known, for example, from the article "A Single-Layer Metal-Electrode CCD Image Sensor" by Nakamura et al., published in the Digest of technical papers of the 1995 IEEE International Solid-State Circuits Conference, pp. 222-223. In this known method, which is used for the manufacture of gates of a CCD, the conductor layer is formed by a WSi layer which is covered with a silicon oxide layer in which a mask is formed for patterning the WSi layer. Auxiliary windows are provided in the oxide layer at the areas of the gaps between the gates to be formed for this purpose, the dimensions of the auxiliary windows being greater than those of the gaps to be eventually obtained. The oxide layer is etched throughout its entire thickness, so that the WSi layer lies exposed in the auxiliary windows. The mask windows of reduced dimensions are obtained through the application of spacers on the side walls of the auxiliary windows.
In the method described here, the silicon oxide layer is etched down to the gates to be formed. This may give rise to problems if the etching selectivity between silicon oxide and the conductor material is not sufficiently great, because in that case the gate material will also be attacked. It is of major importance that the material of the gates should not or at least substantially not be made locally thinner owing to the etching of the silicon oxide layer, especially in cases where the conductor layer is very thin, for example comprises a layer of 60 nm thick polycrystalline silicon (poly) in view of the envisaged photosensitivity of the CCD imager.
The invention accordingly has for its object inter alia to modify a method of the kind mentioned in the opening paragraph in such a manner that the conductor material of the gates is not or substantially not attacked by the etchant for the silicon oxide layer.
A further problem which often arises, at least with the use of polycrystalline silicon as the conductor material, while the gates are formed through etching of poly, is that short-circuits of more or less high-ohmic values occur between the gates after etching of the poly, probably as a result of material remaining behind in the gaps after etching. The invention accordingly has for its further object to provide a method whereby such short-circuits can be prevented while very narrow gaps between the conductor tracks are retained.